Presently the conventional static random-access memory (SRAM) is in the form of a latch composed of two back-to-back, cross-coupled, CMOS inverters. As seen in FIG. 1, one inverter 10 on one side has a PMOS, Mp1, and an NMOS, Mn1, with the PMOS source connected to voltage source Vdd, the NMOS source connected to ground, and their gates and drains respectively connected together. The other inverter 20 on the other side has a similarly connected PMOS and NMOS, Mp2, Mn2, and both inverters have their commonly connected gates connected to the drains of the PMOS and NMOS on the opposite side. These latter connections to the drains form read/write nodes, that are coupled to respective signal carrying lines, Q.about., on the one side, and Q, on the other side Capacitances C1 and C2 are the total node capacitances (including diffusion and routing) and are shown also in the small-signal model equivalent circuit in FIG. 2, wherein Cm is the coupling capacitance between the gates and drains of the MOSFETs. A small-signal analysis of the circuit of FIG. 2 results in the following relationships: EQU g.sub.m1 v2+g.sub.d1 v1+C.sub.1 dv1/dt+C.sub.m d(v1-v2)/dt=0
and EQU g.sub.m2 v1+g.sub.d2 v2+C.sub.2 dv2/dt+C.sub.m d(v2-v1)/dt=0
where
g.sub.m1, g.sub.m2 are equivalent transconductances of M.sub.p1 /M.sub.n1 and M.sub.p2 /M.sub.n2, respectively, and g.sub.d1, g.sub.d2 are equivalent conductances. PA1 G=gd1+gd2+gm1+gm2; PA1 Q=M.sup.2 -4a(gd1gd2-gm1gm2) PA1 g.sub.m1 &gt;g.sub.m2, then Un1&gt;Un2 and V.sub.th1 &lt;V.sub.th2, so Q=low and Q.about.=high; and conversely, when: PA1 g.sub.m1 &lt;g.sub.m2, then Un1&lt;Un2 and V.sub.th1 &gt;V.sub.th2, so Q=high and Q.about.=low.
Applying the LaPlace transforms with appropriate initial conditions the following relationship for the output can be obtained: ##EQU1## where i=1 and j=2 are for .mu..sub.2 (t), while i=2 and j=1 are for .nu..sub.1 (t); ##EQU2## a=C.sub.1 C.sub.2 +C.sub.m (C.sub.1 +C.sub.2); M=gd1C.sub.2 +gd2C.sub.1 +C.sub.m G;
Using the above equation, an important analysis can be carried out. When P1&gt;0 and P2&lt;0, if assuming .tau.&gt;&gt;0, then e.sup.p2t approaches zero. For e.sup.p1t, the latch is assumed symmetrical and when machine is turned on, V.sub.1 (0.sub.--)=V.sub.2 (0.sub.--).
The transconductance terms g.sub.m1 and g.sub.m2 are related to the NMOS mobility values Un1 and Un2, which in turn relate to the NMOS threshold voltages V.sub.th1 and V.sub.th2, such that when:
In a completely symmetrical SRAM cell, if the initial condition of the threshold voltages is V.sub.th1 =V.sub.th2, then Q=Q.about., and a random result is produced, that is, Q may be high or it may be low, and Q.about. may vary similarly as seen in FIG. 1.
Also, in a completely symmetrical SRAM cell, if the initial condition indicates a difference between Q and Q.about. and it is larger than a certain voltage, say 0.5 mV, then a correct result can be generated, i.e., under the initial condition, if Q&gt;Q.about., then the final (steady state) result is that Q is high and Q.about. is low, or if Q&lt;Q.about., then the final result is that Q is low and Q.about. is high, as seen in FIGS. 3-6. In FIG. 3 the initial conditions are Q=0.2005 V and Q.about.=0.2 V, with the final result that Q=high and Q.about.=low. In FIG. 4 the initial conditions are Q=0.2 V and Q.about.=0.2005 V, with the final result that Q=low and Q.about.=high. In FIG. 5 the initial conditions are Q=4.8005 V and Q.about.=4.8 V, with the final result that Q=high and Q.about.=low. In FIG. 6 the initial conditions are Q=4.8 V and Q.about.=4.8005 V, with the final result that Q=low and Q.about.=high.
The random and correct result conditions become an important consideration in a regular or conventional SRAM of the type described because when the system or computer in which it is disposed is turned off or goes down, the originally stored data are extinguished or disappear. This is frequently undesirable, particularly when the system goes down unexpectedly, since when the system is again powered up, the random condition will result with some cells being low, and some being high, so that the stored data is lost unless the initial condition can be made to indicate a difference between Q and Q.about..
It is therefore an object of the present invention to provide an SRAM with the quality of being non-volatile, i.e., its condition will not disappear with time or turn off.
It is another object of the invention to provide an SRAM with the quality of being non-volatile, by deliberately causing the threshold voltages transconductance g.sub.m, mobility .mu.n of the NMOS devices to be different.
It is further object of the invention to provide a non-volatile SRAM by deliberately causing the threshold voltages transconductance g.sub.m, mobility .mu.n of the NMOS devices to be different using the hot electron effect.